1. Field of the Invention
The present invention relates generally to control of clock signals in digital systems such as, for example, integrated circuits (ICs). More particularly, the present invention relates to synchronously multiplexing clock signals for controlling circuit elements in such a system.
2. Description of the Related Art
Most digital systems (e.g., microprocessor chips) operate as control driven, synchronous sequential systems. This means the sequence of operations in the system is synchronized by a master clock signal (usually an external clock). This clock signal is usually one of the form shown in FIG. 1; which illustrates a square wave with a substantially 50% duty cycle.
The master clock signal allows system operations to occur at regularly spaced intervals. In particular, operations are made to take place at times when the clock signal is making a transition from low-to-high or from high-to-low; rising edge 102 or falling edge 104, respectively.
Many microprocessor chips have their timing controlled by two or more related clock signals generated by an on-chip clock generator based on the master clock signal. FIG. 2A illustrates one such combination utilizing two clock signals identified by .phi.1 and .phi.2. This clocking arrangement provides four different edges and three different states per period, compared to only two edges and two states per period provided with a single clock signal as shown in FIG. 1. FIG. 2B illustrates examples of the three possible states for clock signals .phi.1 and .phi.2. For elements on the chip to function properly, it is important that edges of clock signals .phi.1 and .phi.2 are non-overlapping. If the edges overlap there will be more restrictions on data transfer and signal hand shaking.
For the non-overlapping clock signals .phi.1 and .phi.2 shown, the rising edge 202 of clock signal .phi.1 defines the beginning of a .phi.1 clock pulse, and the falling edge 204 defines the end of the .phi.1 clock pulse. Likewise, the rising edge 206 of clock signal .phi.2 defines the beginning of a .phi.2 clock pulse, and the falling edge 208 defines the end of the .phi.2 clock pulse. In STATE 1, both .phi.1 and .phi.2 reside at an inactive clock signal level, in this case a logic "0". Only one clock at a time is driven to an active clock signal level (e.g., a logic "1"). Complement clock signals, where only one phase at a time ever resides at a logic "0", are also entirely possible.
Additionally, it is equally important that non-overlapping clock pulses be evenly distributed to all corners of a chip regardless of the distance which those signals must travel. As chip size increases, clock signals .phi.1 and .phi.2 have to travel greater distances throughout the chip. This causes clock signals .phi.1 and .phi.2 to become degraded. As distances increase, rising edges 202, 206 and falling edges 204, 208 may become obscured (experience phase shifts and increases in transition times) and can overlap. This phenomenon, sometimes referred to as clock skew, is caused by a number of factors, including: loading, unwanted noise, coupling, capacitance, resistance, inductance and other debilitating effects.
To account for these factors, designers must separate the rising and falling edges 202, 204, 206, 208 of different clock signals (i.e., .phi.1 and .phi.2) with a large enough margin of time to allow for clock skew. For instance, falling edge 204 and rising edge 206 must be separated by a minimum temporal distance or amount of time (T) to avoid overlapping states; especially for level-triggering operations in metaloxide-silicon (MOS) technology. The larger T is, the less likely the chip will fail due to overlapping signals caused by skewing. The wide range of operating environments to which the chip(s) may be subject must be considered in selecting T. Therefore, to provide an adequate margin, manufacturers are forced to select T large enough to provide functionality in a worst-case environment. However, a large T is a significant cycle time constraint.
For this reason, two-phase non-overlapping clock signals are frequently generated on-chip, so that chip-to-chip I/O delays and skews do not add to the clock skew between clock phases. Clock frequency can be more easily increased and T reduced by using a two-phase clock generator on-board the integrated circuit itself, which is typically supplied with a single-phase externally-generated clock signal.
The testing of microprocessor integrated circuits presents many problems, including the synchronization of internal operation, while testing, with externally applied stimuli such as test vectors. Consequently, it is sometimes desirable to clock a microprocessor under testing conditions with externally supplied test clock signals rather than the internally generated clock signals normally utilized. But since many operations must be tested at full speed, and since it is difficult to externally clock the integrated circuit as fast as the internal clock signals may be operated, the integrated circuit must also be tested using the internally generated system clocks. Moreover, it is frequently desirable to clock the integrated circuit with test clocks and external stimuli to pre-condition certain portions of the integrated circuit under test, or to provide certain arguments, or to present certain conditions to portions of the integrated circuit under test. Subsequent to such pre-conditioning, the integrated circuit is clocked with system clocks to perform the at-speed test in question.
If, when the clock signals within the integrated circuit are transferred from the test clock signals to the system clock signals, certain clock "glitches" or narrow clocks occur, then the integrated circuit may malfunction and mar the validity of the test. What is needed, for example, is a clock signal multiplexer which affords synchronous transfer of clock signals, as would be provided internally to an integrated circuit, from a pair of non-overlapping test clock signals to a pair of non-overlapping system clock signals.